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[Com Port] uart16750_latest.tar

Description: Implements a 16550/16750 UART core
Platform: | Size: 100352 | Author: Arun | Hits:

[Other] ISO16750_1

Description: iso 16750-1ISO (the International Organization for Standardization) is a worldwide federation of national standards bodies (ISO member bodies).
Platform: | Size: 524288 | Author: 江文杰 | Hits:

[VHDL-FPGA-Verilog] uart16750

Description: UART 16750 source code for VHDL
Platform: | Size: 151552 | Author: maxshao | Hits:

[VHDL-FPGA-Verilog] uart16750_latest.tar

Description: UART 16750 VHDL core
Platform: | Size: 137216 | Author: Joe | Hits:

[MPI] uart16750_latest[1].tar

Description: uart 16750 core discripe with VHDL language
Platform: | Size: 137216 | Author: asdtgg | Hits:

[3G develop] uart16750_latest.tar

Description: UART 16750 Source Code
Platform: | Size: 137216 | Author: ByoungSoo | Hits:

[VHDL-FPGA-Verilog] uart16750_latest.tar

Description: Implements a synthesizable 16550/16750 UART core.
Platform: | Size: 137216 | Author: Juanjo | Hits:

[VHDL-FPGA-Verilog] wb_uart_latest.tar

Description: 实现一个一16750/16550 UART。该UART内核是完全基于另一个OpenCores的项目：UART_16750塞巴斯蒂安维特。 请找到有关于UART内核的文档。 该接口是现在有8位Wishbone总线兼容。 随着GHDL模拟器只需运行： ./ghdl_uart.bat 使用任何其他模拟器，开始模拟以下perl脚本必须运行之前： uart_test_stim.pl> FILENAME.TXT 其中，FILENAME.TXT是通用的“stim_file”选择内部wb8_uart_transactor.vhd的名称。 正确的模拟应退出并断言消息“模拟END”。-Implements a 16550/16750 UART. The UART core is fully based on another OpenCores project: UART_16750 by Sebastian Witt. Please find there the documentation regarding the Uart core. The interface is now compatible with a 8-bit WishBone bus. With GHDL simulator simply run: ./ghdl_uart.bat Using any other simulator, before starting the simulation the following perl script must be run: uart_test_stim.pl > filename.txt where filename.txt is the name selected in generic stim_file inside wb8_uart_transactor.vhd. A correct simulation should exit with an assertion message simulation END .
Platform: | Size: 21504 | Author: 包 | Hits:

[VHDL-FPGA-Verilog] UART_16750_vhdl

Description: UART串口FPGA源文件，VHDL设计文件，兼容16750-UART FPGA VHDL 16750
Platform: | Size: 23552 | Author: yp | Hits:

[LabView] 16750

Description: 通过电源实现ISO16750波形输出，满足汽车电子波形的测试要求(ISO16750 waveform output is realized by power supply to meet the test requirements of automobile electronic waveform)
Platform: | Size: 4136960 | Author: 柯东 | Hits:

[Documents] ISO 16750

Description: ISO 16750 标准共分为五个部分，除第一部分通则之外，其余四个部分分别为电力负载、 机械负载、气候负载及化学负载，另外，针对其电源系统分可适用于 12 伏特(乘客车)及 24 伏特(商用车)两类，而碍于篇幅限制，本文将仅针对使用占比较大之乘客车(Passenger Car)12 伏特系统来分别依据四项负载要求做说明。(The ISO 16750 standard is divided into five parts. The first part except for the rest of the four parts are the power load, mechanical load, climate load and chemical load, in addition, the power system can be applied to 12 volts and 24 volts (passenger) (commercial vehicle) two, but due to space this paper will use restrictions, only for a larger proportion of passenger cars (Passenger Car) 12 volt system respectively according to four load requirements description.)
Platform: | Size: 1981440 | Author: 飞翔的小小玉 | Hits:

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