Description: 数字电子钟程序，计时时、分、秒，手动调整时间，闹铃，和整点报时-digital electronic clock procedures, a time when, minutes, and seconds, manual adjustments, Alarms, and the whole point is true. Platform: |
Size: 1024 |
Author:傻航 |
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Description: 朋友，我是Jawen.看到先前上载的一套CPLD开发板的VHDL源码挺受欢迎的，现在就将她的Verilog源码也一并贡献给大家：8位优先编码器,乘法器,多路选择器,二进制转BCD码,加法器,减法器,简单状态机,四位比较器,7段数码管,i2c总线,lcd液晶显示,拨码开关,串口,蜂鸣器,矩阵键盘,跑马灯,交通灯,数字时钟-friends, I Jawen. previously seen on the set of CPLD Development Board VHDL source code quite welcome, Now she will also be Verilog source contribution to everyone : eight priority encoder, multipliers, Multi-channel selector, binary to BCD, adder, subtraction device, the simple state machine, four comparators, 7 of the digital control, i2c bus, lcd LCD allocated code switches, serial port, the buzzer sounded, matrix keyboards, Bomadeng. Traffic lights, digital clock Platform: |
Size: 3151872 |
Author:Jawen |
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Description: 51单片机数字时钟(汇编程序原代码),包括按键调时间等功能.-51 single-chip digital clock (the original assembler code), including key features such as transfer time. Platform: |
Size: 7168 |
Author:何平 |
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Description: 基于AT89S52的自动报时数字闹钟.
该数字钟具有整点报时和闹钟功能，时间显示为 时.分.秒，以12小时制显示。可通过按键调整时间的小时位和分钟位，整点和闹钟均以闪烁方式报时。
程序分为以下模块：数码管显示模块，控制显示模块，定时器T0中断处理模块，定时器T1中断处理模块，键盘扫描模块，键盘处理模块，延时模块和整点闪烁模块-AT89S52 based on automatic timekeeping digital alarm clock. The whole point of digital clock with timer and alarm clock function, time display too. Sub. Seconds to 12-hour show. Buttons adjust the time by the hour and minute-bit-bit, the whole point and the alarm time are blinking manner. Procedures are divided into the following modules: digital tube display module, control module, processing module interrupt timer T0, T1 timer interrupt handling module, the keyboard scan module, the keyboard processing module, delay module and the whole point of flashing module Platform: |
Size: 3072 |
Author:陈 |
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Description: 【设计题目】
多功能数字钟的设计
【设计目的】
1掌握数字系统的分析和设计方法
2能够熟练的、合理的选用集成电路器件
3熟悉EWB软件的使用。
【设计指标及要求】
设计一个多功能数字钟，以一昼夜24小时为一个计数周期。准确计时，具有“时”“分”“秒”数字显示。整点能自动打点、报时。要求报时声响四低一高，最后一响为整点。具有校时功能。要求电路主要采用中小规模CMOS集成电路。要求电路尽量简化，并选用同类型的器件。在EWB电子工作平台上进行电路的设计和计算机仿真。
-Title] [design multi-functional digital clock design 1] [designed to exploit the digital system analysis and design method of 2 to skilled, reasonable choice of integrated circuit device 3 familiar with the EWB software. [] Design specifications and requirements to design a multi-function digital clock, 24 hours a day for a cycle count. Accurate time, a when sub seconds The figures show. Automatically runs the whole point, the newspaper. Four-time low noise requirements of a high, the final point for the whole ring. With a school function. Requirements are mainly small and medium-sized circuits CMOS integrated circuits. Asked the circuit as simple as possible and select the same type of device. EWB work in the platform of electronic circuit design and computer simulation. Platform: |
Size: 197632 |
Author:petyfer |
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Description: JXARM9-2410 实时时钟实验主程序
完成功能:
时钟滴答:每秒钟刷新数码管显示
设置当前日期、时间
动态刷新当前日期、时间。
时间告警功能:每分钟的第5秒告警，并进行跑马灯显示。-JXARM9-2410 real-time clock to complete the experiment the main program functions: the clock ticking: second refresh digital tube display settings the current date, time, dynamic refresh current date, time. Time alarm function: per minute, 5 seconds of the first alarm, and Marquee show. Platform: |
Size: 81920 |
Author:伟建 |
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Description: 一个精致的数字时钟程序。有万年历，提醒等功能。-A sophisticated digital clock procedures. There are calendar, reminder functions. Platform: |
Size: 113664 |
Author:tom |
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Description: 用VERILOG编写的数字电子钟，用数码管进行显示时间-VERILOG prepared with digital electronic clock with a nixie tube display time Platform: |
Size: 3072 |
Author:黄涛 |
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Description: Quartus II工程压缩文件，是一个典型的基于FPGA的数字钟工程项目，有50MHz分频、计数、译码等模块。采用VHDL语言编写。-Quartus II project files, is a typical FPGA-based digital clock project, there are sub-50MHz frequency, counting, decoding modules. Using VHDL language. Platform: |
Size: 652288 |
Author:kg21kg |
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Description: VerilogHDL程序，功能是可以实现一个数字电子时钟。-It s a Verilog-HDL procedure which can makes a digital electronic clock. Platform: |
Size: 81920 |
Author:朱惠雅 |
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Description: LCDTimer.rar，是Protues仿真的c程序，主要功能是显示数字时钟，-LCDTimer.rar, is Protues c simulation program, the main function is to display digital clock Platform: |
Size: 12288 |
Author:gezhuag |
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Description: 可实现数字钟的基本功能，有定时，闹铃，整点报时等功能-have the basic function of digital clock,including timing,alarm clock,NowTime Platform: |
Size: 6144 |
Author:xiaodong |
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Description: 创建显示数字钟的静态文本框\PicClockDemo\PicClockDemo.rar,很不错的vc源码，希望对大家有所帮助。-Create a digital clock display static text box \ PicClockDemo \ PicClockDemo.rar, very good vc source code, we want to help. Platform: |
Size: 33792 |
Author: |
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Description: 设计FPGA电路以模拟多功能电子表的工作过程，功能如下：（1 ）数字钟，要求从00：00 ：00点计到23 ：59：59 （2）数字跑表（3 ）调整时间 (4)闹钟设置，可以设置2个闹钟，闹钟时间到了后会提醒，提醒时间持续20 秒，如果此时按A键，则该闹钟解除提醒，如果按住B键，闹钟暂停提醒。但是3 分钟后重复提醒一次。如果闹钟响时没有按键，则响完20秒之后暂停，然后同样3 分钟后重新提醒一次。（5 ）日期设置。可以设置当前的日期，
比如2012年08月20 日。-Design FPGA circuits to analog the multifunctional electronic table work process, the following functions: (1) digital clock count: 00 points from 00:00 to 23: 59:59 (2) digital the stopwatch (3) to adjust the time (4 ) set the alarm clock, can set two alarm clock, alarm time to remind reminder time for 20 seconds, then press the A key, the alarm clock lifted reminder, if you hold down the B button, snooze alert. But three minutes later repeated reminder. If the alarm goes off, no buttons, sound finished 20 seconds after the pause, and then the same three minutes after the re-remind once. (5) The date is set. Can be set to the current date, such as the August 20, 2012. Platform: |
Size: 1664000 |
Author:章梓音 |
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