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Description: interleaver即交织器，里面包含有C,VHDL,VRILOG HDL三种语言写的交织器,
包括各种各样的组合达六七十种，描写详尽，是一个难得的学习交织器的材料
-interleaver that interleaver, which contains C, VHDL, VRILOG HDL three languages to write the interleaver, including a variety of combinations to depend species, a detailed description, is a rare study of the materials are intertwined
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Size: 360448 |
Author: 陈朋 |
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Description: verilog HDL语言实现dvb_t中的比特交织器源代码描述-verilog HDL language dvb_t the bit interleaver source code Description
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Size: 1024 |
Author: wenjuner |
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Description: 基于FPGA的Turbo码交织器的设计与实现
比较实用-FPGA-Based Turbo Code Interleaver Design and Implementation of a more practical
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Size: 371712 |
Author: mediative |
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Description: 由RS码、卷积码构成的级联码，结合交织技术，用于信道编码-RS code and convolution code, combine with interleaving, use for channel coding.
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Size: 4096 |
Author: 娜 |
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Description: documents for qpp interleaver for turbo coding
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Size: 617472 |
Author: ren |
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