Welcome![Sign In][Sign Up]
Location:
Downloads SourceCode/Document Embeded-SCM Develop VHDL-FPGA-Verilog
Title: rs232_verilog Download
 Description: The receiver is a serial receiving module, receiving from serial port receives the serial data sent by the host computer, and gives a notification signal after receiving a frame of data (8 bits) done. The Sender is the serial port sending module, is the core. In order to send the enable signal, the received data is data send port through serial port is sent out. It should be noted that there are two variables defined in the top module, system clock frequency Freq and BPS is used according to the different system clock frequency and the required serial port baud rate. We can try to the serial port baud is set to other values (such as 9600). When the module is instantiated, this variable will be passed to the serial port receiving and sending module, so as to achieve different rates of serial communication.
 Downloaders recently: [More information of uploader bigpin2021]
 To Search:
File list (Click to check if it's the file you need, and recomment it at the bottom):
文件名大小更新时间
uart_send.v 3462 2021-01-26
uart_recv.v 3713 2021-01-26

CodeBus www.codebus.net