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Title: mul64 Download
  • Category:
  • HardWare Design
  • Platform:
  • Verilog
  • File Size:
  • 1714176
  • Update:
  • 2021-01-11
  • Downloads:
  • 0
  • Uploaded by:
  • 遥风
 Description: The 64 bit binary integer multiplier is designed and implemented by Verilog HDL. The bottom multiplier is implemented by 16 * 16, 8 * 8, 8 * 32 and 8 * 16 small bit width multiplier. The bottom multiplier is implemented by FPGA internal IP
 Downloaders recently: [More information of uploader 遥风]
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File list (Click to check if it's the file you need, and recomment it at the bottom):
文件名大小更新时间
64bits算术乘法器.docx 1794235 2021-01-11
mul16.v 4461 2020-05-16
multiplier_64.v 6637 2020-05-17
multiplier_64_tb.v 619 2020-05-17

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