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Description: When using asynchronous signals, a good design will perform synchronous processing on asynchronous signals. Synchronization generally uses multi-level D flip-flop cascade processing, as shown in the figure below. Most of the data of this model say that after the first-level register generates a metastable state, the second-level register has a stable output probability of 90%, and the third-level register has a stable output probability of 99%. If the metastable state follows the circuit, Pass it on, and the system with weaker self-repair ability will directly collapse.
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|fft.txt|| 3922 || 2020-11-17
|异步FIFO.v|| 2408 || 2020-09-05|