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Title: test6 Download
 Description: In this design, a 16 bit binary adder designed in time sequence is composed of 3 stages of pipelined 16 bit adder, hexadecimal addition counter and 16 bit three state control gate circuit. This design is a 3-stage pipeline design, which increases the delay of the inserted registers and the time difference of signal synchronization, but it can improve the overall running speed. In use, you only need to input the addend and the addend. Press the first equal key to save the first addition result. Press the second equal key to get the first addition result. At the same time, store the second result. Press the third equal key to get the result of the second addition. The result is stable and can meet the design requirements of pipelined 16 bit add
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文件名大小更新时间
test6\adder16.bsf 2342 2019-11-20
test6\adder16.cmp 1186 2019-11-18
test6\adder16.inc 1223 2019-11-18
test6\adder16.qpf 1295 2019-11-12
test6\adder16.qsf 5576 2019-11-24
test6\adder16.qws 1391 2019-11-24
test6\adder16.vhd 1237 2019-11-20
test6\adder16.vhd.bak 808 2019-11-12
test6\adder16.vwf 22224 2019-11-24
test6\adder16.vwf.temp 22224 2019-11-24
test6\block1.vhd 2713 2019-11-18
test6\Block3.bdf 12590 2019-11-20
test6\Block3.vhd 2742 2019-11-20
test6\c5_pin_model_dump.txt 2857 2019-11-18
test6\cio_dump_disallowed_lists.echo 53139 2019-11-18
test6\cnt10.bsf 1952 2019-11-12
test6\cnt10.inc 1200 2019-11-12
test6\cnt10.vhd 503 2019-11-12
test6\cnt10.vhd.bak 489 2019-11-12
test6\cnt10.vwf 9553 2019-11-24
test6\cnt10.vwf.temp 9553 2019-11-24
test6\db\adder16.(0).cnf.cdb 2475 2019-11-18
test6\db\adder16.(0).cnf.hdb 1299 2019-11-18
test6\db\adder16.(1).cnf.cdb 1414 2019-11-18
test6\db\adder16.(1).cnf.hdb 841 2019-11-18
test6\db\adder16.(2).cnf.cdb 4333 2019-11-20
test6\db\adder16.(2).cnf.hdb 2027 2019-11-20
test6\db\adder16.(3).cnf.cdb 2302 2019-11-20
test6\db\adder16.(3).cnf.hdb 959 2019-11-20
test6\db\adder16.asm.qmsg 2517 2019-11-24
test6\db\adder16.asm.rdb 1435 2019-11-24
test6\db\adder16.asm_labs.ddb 29783 2019-11-24
test6\db\adder16.cbx.xml 89 2019-11-24
test6\db\adder16.cmp.bpm 962 2019-11-24
test6\db\adder16.cmp.cdb 31747 2019-11-24
test6\db\adder16.cmp.hdb 15507 2019-11-24
test6\db\adder16.cmp.idb 12102 2019-11-24
test6\db\adder16.cmp.kpt 217 2019-11-24
test6\db\adder16.cmp.logdb 21751 2019-11-24
test6\db\adder16.cmp.rdb 22793 2019-11-24
test6\db\adder16.cmp_merge.kpt 222 2019-11-24
test6\db\adder16.cuda_io_sim_cache.31um_ff_1200mv_0c_fast.hsd 388851 2019-11-24
test6\db\adder16.cuda_io_sim_cache.31um_ss_1200mv_85c_slow.hsd 380251 2019-11-24
test6\db\adder16.cyclonev_io_sim_cache.ff_0c_fast.hsd 1052492 2019-11-18
test6\db\adder16.cyclonev_io_sim_cache.ff_85c_fast.hsd 1053277 2019-11-18
test6\db\adder16.cyclonev_io_sim_cache.ii_0c_slow.hsd 1062513 2019-11-18
test6\db\adder16.cyclonev_io_sim_cache.ii_85c_slow.hsd 1053521 2019-11-18
test6\db\adder16.db_info 155 2020-11-18
test6\db\adder16.eda.qmsg 2516 2019-11-24
test6\db\adder16.eds_overflow 2 2019-11-24
test6\db\adder16.fit.qmsg 59387 2019-11-24
test6\db\adder16.fnsim.cdb 8494 2019-11-24
test6\db\adder16.fnsim.hdb 15112 2019-11-24
test6\db\adder16.fnsim.qmsg 7306 2019-11-24
test6\db\adder16.hier_info 11534 2019-11-24
test6\db\adder16.hif 576 2019-11-24
test6\db\adder16.ipinfo 178 2020-11-18
test6\db\adder16.lpc.html 1379 2019-11-24
test6\db\adder16.lpc.rdb 511 2019-11-24
test6\db\adder16.lpc.txt 2332 2019-11-24
test6\db\adder16.map.ammdb 138 2019-11-24
test6\db\adder16.map.bpm 923 2019-11-24
test6\db\adder16.map.cdb 8323 2019-11-24
test6\db\adder16.map.hdb 13899 2019-11-24
test6\db\adder16.map.kpt 2789 2019-11-24
test6\db\adder16.map.logdb 4 2019-11-24
test6\db\adder16.map.qmsg 8717 2019-11-24
test6\db\adder16.map.rdb 1339 2019-11-24
test6\db\adder16.map_bb.cdb 1998 2019-11-24
test6\db\adder16.map_bb.hdb 9848 2019-11-24
test6\db\adder16.map_bb.logdb 4 2019-11-24
test6\db\adder16.pplq.rdb 247 2019-11-24
test6\db\adder16.pre_map.hdb 13430 2019-11-24
test6\db\adder16.pti_db_list.ddb 192 2019-11-24
test6\db\adder16.root_partition.map.reg_db.cdb 213 2019-11-24
test6\db\adder16.routing.rdb 13959 2019-11-24
test6\db\adder16.rpp.qmsg 2143 2019-11-22
test6\db\adder16.rtlv.hdb 13362 2019-11-24
test6\db\adder16.rtlv_sg.cdb 7527 2019-11-24
test6\db\adder16.rtlv_sg_swap.cdb 1393 2019-11-24
test6\db\adder16.sgate.rvd 3434 2019-11-22
test6\db\adder16.sgate_sm.rvd 235 2019-11-22
test6\db\adder16.sgdiff.cdb 8311 2019-11-24
test6\db\adder16.sgdiff.hdb 13403 2019-11-24
test6\db\adder16.sim.hdb 4796 2019-11-24
test6\db\adder16.sim.qmsg 5691 2019-11-24
test6\db\adder16.sim.rdb 7948 2019-11-24
test6\db\adder16.sim.vwf 18072 2019-11-24
test6\db\adder16.simfam 10 2019-11-24
test6\db\adder16.sld_design_entry.sci 217 2020-11-18
test6\db\adder16.sld_design_entry_dsc.sci 217 2019-11-24
test6\db\adder16.smart_action.txt 8 2019-11-24
test6\db\adder16.sta.qmsg 19311 2019-11-24
test6\db\adder16.sta.rdb 55904 2019-11-24
test6\db\adder16.syn_hier_info 0 2019-11-24
test6\db\adder16.tiscmp.fast_1200mv_0c.ddb 169015 2019-11-24
test6\db\adder16.tiscmp.slow_1200mv_0c.ddb 170620 2019-11-24
test6\db\adder16.tiscmp.slow_1200mv_85c.ddb 170972 2019-11-24
test6\db\adder16.tis_db_list.ddb 257 2019-11-24
test6\db\adder16.vpr.ammdb 559 2019-11-24

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