Welcome![Sign In][Sign Up]
Downloads SourceCode/Document Embeded-SCM Develop VHDL-FPGA-Verilog
Title: rtl Download
 Description: FPGA USART transmit & receive module,where EN signal indicates the begging of transmit.The data width:8Bits
 To Search:
File list (Click to check if it's the file you need, and recomment it at the bottom):
uart_r.v 2912 2020-04-28
uart_t.v 2778 2020-10-12

CodeBus www.codebus.net