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Description: In this paper, an efficient storage method for quasi cyclic LDPC decoder with partially parallel structure is proposed, which stores the decoded quasi code words in channel information and external information storage blocks. This method can reduce the storage resource requirement of the decoder and reduce the wiring complexity of decoding circuit. In addition, this paper analyzes the LDPC code by analyzing the performance of the decoder In this paper, we propose a dynamic address access management method based on the structure. The decoder can be implemented in parallel with the variable node processing unit and the check node processing unit
In this paper, a LDPC decoder design method with variable iterations is proposed, which can reduce the total clock cycles required for decoding, and is suitable for decoder implementation with high real-time requirements .
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|_LDPC码的高效编译码实现技术研究.caj|| 1802794 || 2020-09-12|