Welcome![Sign In][Sign Up]
Location:
Downloads SourceCode/Document Embeded-SCM Develop VHDL-FPGA-Verilog
Title: Single-CPU Download
 Description: Simple single-cycle CPU design,The instructions implemented are as follows:Arithmetic operation instruction, logical operation instruction, shift instruction, comparison instruction, memory read/write instruction, branch instruction, jump instruction, stop instruction.
 Downloaders recently: [More information of uploader 蓝湛506]
 To Search:
File list (Click to check if it's the file you need, and recomment it at the bottom):
文件名大小更新时间
project_2_singleCPU\CPU_single_sim_behav.wcfg 7097 2018-11-25
project_2_singleCPU\hs_err_pid11716.dmp 322115 2018-11-27
project_2_singleCPU\hs_err_pid11716.log 143 2018-11-27
project_2_singleCPU\instruction.txt 775 2018-11-21
project_2_singleCPU\project_2_singleCPU.cache\wt\gui_handlers.wdf 9723 2019-07-19
project_2_singleCPU\project_2_singleCPU.cache\wt\java_command_handlers.wdf 2033 2019-07-19
project_2_singleCPU\project_2_singleCPU.cache\wt\project.wpc 62 2019-07-19
project_2_singleCPU\project_2_singleCPU.cache\wt\synthesis.wdf 5394 2018-11-19
project_2_singleCPU\project_2_singleCPU.cache\wt\synthesis_details.wdf 100 2018-11-19
project_2_singleCPU\project_2_singleCPU.cache\wt\webtalk_pa.xml 8340 2019-07-19
project_2_singleCPU\project_2_singleCPU.cache\wt\xsim.wdf 256 2018-11-25
project_2_singleCPU\project_2_singleCPU.hw\project_2_singleCPU.lpr 290 2018-11-22
project_2_singleCPU\project_2_singleCPU.ip_user_files\README.txt 130 2018-11-19
project_2_singleCPU\project_2_singleCPU.runs\impl_1\init_design.pb 1689 2018-11-19
project_2_singleCPU\project_2_singleCPU.runs\impl_1\opt_design.pb 7534 2018-11-19
project_2_singleCPU\project_2_singleCPU.runs\impl_1\place_design.pb 19224 2018-11-19
project_2_singleCPU\project_2_singleCPU.runs\synth_1\vivado.pb 63642 2018-11-19
project_2_singleCPU\project_2_singleCPU.sim\sim_1\behav\compile.bat 659 2018-06-10
project_2_singleCPU\project_2_singleCPU.sim\sim_1\behav\compile.sh 1062 2018-06-10
project_2_singleCPU\project_2_singleCPU.sim\sim_1\behav\CPU_single_sim.prj 1297 2018-06-10
project_2_singleCPU\project_2_singleCPU.sim\sim_1\behav\CPU_single_sim.tcl 446 2018-06-10
project_2_singleCPU\project_2_singleCPU.sim\sim_1\behav\CPU_single_sim_behav.log 48 2018-06-10
project_2_singleCPU\project_2_singleCPU.sim\sim_1\behav\CPU_single_sim_behav.wdb 56767 2018-06-10
project_2_singleCPU\project_2_singleCPU.sim\sim_1\behav\xelab.log 4008 2018-06-10
project_2_singleCPU\project_2_singleCPU.sim\sim_1\behav\xelab.pb 7107 2018-06-10
project_2_singleCPU\project_2_singleCPU.sim\sim_1\behav\xsim\compile.bat 846 2018-11-25
project_2_singleCPU\project_2_singleCPU.sim\sim_1\behav\xsim\compile.log 3670 2018-11-25
project_2_singleCPU\project_2_singleCPU.sim\sim_1\behav\xsim\CPU_single_sim.tcl 460 2018-11-25
project_2_singleCPU\project_2_singleCPU.sim\sim_1\behav\xsim\CPU_single_sim_behav.wdb 38862 2018-11-25
project_2_singleCPU\project_2_singleCPU.sim\sim_1\behav\xsim\CPU_single_sim_vlog.prj 1273 2018-11-25
project_2_singleCPU\project_2_singleCPU.sim\sim_1\behav\xsim\elaborate.bat 923 2018-11-25
project_2_singleCPU\project_2_singleCPU.sim\sim_1\behav\xsim\elaborate.log 1377 2018-11-25
project_2_singleCPU\project_2_singleCPU.sim\sim_1\behav\xsim\glbl.v 1474 2018-04-04
project_2_singleCPU\project_2_singleCPU.sim\sim_1\behav\xsim\simulate.bat 903 2018-11-25
project_2_singleCPU\project_2_singleCPU.sim\sim_1\behav\xsim\simulate.log 50 2018-11-25
project_2_singleCPU\project_2_singleCPU.sim\sim_1\behav\xsim\webtalk.jou 1053 2018-11-25
project_2_singleCPU\project_2_singleCPU.sim\sim_1\behav\xsim\webtalk.log 1512 2018-11-25
project_2_singleCPU\project_2_singleCPU.sim\sim_1\behav\xsim\webtalk_10528.backup.jou 1053 2018-11-23
project_2_singleCPU\project_2_singleCPU.sim\sim_1\behav\xsim\webtalk_10528.backup.log 1620 2018-11-23
project_2_singleCPU\project_2_singleCPU.sim\sim_1\behav\xsim\webtalk_11588.backup.jou 1053 2018-11-25
project_2_singleCPU\project_2_singleCPU.sim\sim_1\behav\xsim\webtalk_11588.backup.log 1230 2018-11-25
project_2_singleCPU\project_2_singleCPU.sim\sim_1\behav\xsim\webtalk_12812.backup.jou 1053 2018-11-22
project_2_singleCPU\project_2_singleCPU.sim\sim_1\behav\xsim\webtalk_12812.backup.log 1512 2018-11-22
project_2_singleCPU\project_2_singleCPU.sim\sim_1\behav\xsim\webtalk_12916.backup.jou 1053 2018-11-22
project_2_singleCPU\project_2_singleCPU.sim\sim_1\behav\xsim\webtalk_12916.backup.log 1512 2018-11-22
project_2_singleCPU\project_2_singleCPU.sim\sim_1\behav\xsim\webtalk_4264.backup.jou 962 2018-11-22
project_2_singleCPU\project_2_singleCPU.sim\sim_1\behav\xsim\webtalk_4264.backup.log 1403 2018-11-22
project_2_singleCPU\project_2_singleCPU.sim\sim_1\behav\xsim\xelab.pb 3091 2018-11-25
project_2_singleCPU\project_2_singleCPU.sim\sim_1\behav\xsim\xsim.dir\CPU_single_sim_behav\Compile_Options.txt 262 2018-11-25
project_2_singleCPU\project_2_singleCPU.sim\sim_1\behav\xsim\xsim.dir\CPU_single_sim_behav\obj\xsim_0.win64.obj 58208 2018-11-25
project_2_singleCPU\project_2_singleCPU.sim\sim_1\behav\xsim\xsim.dir\CPU_single_sim_behav\obj\xsim_1.c 7297 2018-11-25
project_2_singleCPU\project_2_singleCPU.sim\sim_1\behav\xsim\xsim.dir\CPU_single_sim_behav\obj\xsim_1.win64.obj 5076 2018-11-25
project_2_singleCPU\project_2_singleCPU.sim\sim_1\behav\xsim\xsim.dir\CPU_single_sim_behav\TempBreakPointFile.txt 29 2018-11-25
project_2_singleCPU\project_2_singleCPU.sim\sim_1\behav\xsim\xsim.dir\CPU_single_sim_behav\webtalk\.xsim_webtallk.info 65 2018-11-25
project_2_singleCPU\project_2_singleCPU.sim\sim_1\behav\xsim\xsim.dir\CPU_single_sim_behav\webtalk\usage_statistics_ext_xsim.html 3666 2018-11-25
project_2_singleCPU\project_2_singleCPU.sim\sim_1\behav\xsim\xsim.dir\CPU_single_sim_behav\webtalk\usage_statistics_ext_xsim.wdm 1117 2018-11-25
project_2_singleCPU\project_2_singleCPU.sim\sim_1\behav\xsim\xsim.dir\CPU_single_sim_behav\webtalk\usage_statistics_ext_xsim.xml 3571 2018-11-25
project_2_singleCPU\project_2_singleCPU.sim\sim_1\behav\xsim\xsim.dir\CPU_single_sim_behav\webtalk\xsim_webtalk.tcl 3865 2018-11-25
project_2_singleCPU\project_2_singleCPU.sim\sim_1\behav\xsim\xsim.dir\CPU_single_sim_behav\xsim.dbg 24104 2018-11-25
project_2_singleCPU\project_2_singleCPU.sim\sim_1\behav\xsim\xsim.dir\CPU_single_sim_behav\xsim.mem 7476 2018-11-25
project_2_singleCPU\project_2_singleCPU.sim\sim_1\behav\xsim\xsim.dir\CPU_single_sim_behav\xsim.reloc 3825 2018-11-25
project_2_singleCPU\project_2_singleCPU.sim\sim_1\behav\xsim\xsim.dir\CPU_single_sim_behav\xsim.rlx 858 2018-11-25
project_2_singleCPU\project_2_singleCPU.sim\sim_1\behav\xsim\xsim.dir\CPU_single_sim_behav\xsim.rtti 323 2018-11-25
project_2_singleCPU\project_2_singleCPU.sim\sim_1\behav\xsim\xsim.dir\CPU_single_sim_behav\xsim.svtype 93 2018-11-25
project_2_singleCPU\project_2_singleCPU.sim\sim_1\behav\xsim\xsim.dir\CPU_single_sim_behav\xsim.type 24 2018-11-25
project_2_singleCPU\project_2_singleCPU.sim\sim_1\behav\xsim\xsim.dir\CPU_single_sim_behav\xsim.xdbg 17920 2018-11-25
project_2_singleCPU\project_2_singleCPU.sim\sim_1\behav\xsim\xsim.dir\CPU_single_sim_behav\xsimcrash.log 0 2018-11-25
project_2_singleCPU\project_2_singleCPU.sim\sim_1\behav\xsim\xsim.dir\CPU_single_sim_behav\xsimk.exe 110839 2018-11-25
project_2_singleCPU\project_2_singleCPU.sim\sim_1\behav\xsim\xsim.dir\CPU_single_sim_behav\xsimkernel.log 336 2018-11-25
project_2_singleCPU\project_2_singleCPU.sim\sim_1\behav\xsim\xsim.dir\CPU_single_sim_behav\xsimSettings.ini 1153 2018-11-25
project_2_singleCPU\project_2_singleCPU.sim\sim_1\behav\xsim\xsim.dir\xil_defaultlib\@a@l@u.sdb 2837 2018-11-25
project_2_singleCPU\project_2_singleCPU.sim\sim_1\behav\xsim\xsim.dir\xil_defaultlib\@c@p@u_single.sdb 5317 2018-11-25
project_2_singleCPU\project_2_singleCPU.sim\sim_1\behav\xsim\xsim.dir\xil_defaultlib\@c@p@u_single_sim.sdb 2427 2018-11-25
project_2_singleCPU\project_2_singleCPU.sim\sim_1\behav\xsim\xsim.dir\xil_defaultlib\@control@unit.sdb 11460 2018-11-25
project_2_singleCPU\project_2_singleCPU.sim\sim_1\behav\xsim\xsim.dir\xil_defaultlib\@data@memory.sdb 2425 2018-11-25
project_2_singleCPU\project_2_singleCPU.sim\sim_1\behav\xsim\xsim.dir\xil_defaultlib\@instrucion@memory.sdb 1618 2018-11-25
project_2_singleCPU\project_2_singleCPU.sim\sim_1\behav\xsim\xsim.dir\xil_defaultlib\@j@u@m@p.sdb 810 2018-11-25
project_2_singleCPU\project_2_singleCPU.sim\sim_1\behav\xsim\xsim.dir\xil_defaultlib\@multiplexer32@for4.sdb 1548 2018-11-25
project_2_singleCPU\project_2_singleCPU.sim\sim_1\behav\xsim\xsim.dir\xil_defaultlib\@multiplexer32@for@a.sdb 996 2018-11-25
project_2_singleCPU\project_2_singleCPU.sim\sim_1\behav\xsim\xsim.dir\xil_defaultlib\@multiplexer32@for@b.sdb 814 2018-11-25
project_2_singleCPU\project_2_singleCPU.sim\sim_1\behav\xsim\xsim.dir\xil_defaultlib\@multiplexer32@for@d@b.sdb 812 2018-11-25
project_2_singleCPU\project_2_singleCPU.sim\sim_1\behav\xsim\xsim.dir\xil_defaultlib\@multiplexer5.sdb 779 2018-11-25
project_2_singleCPU\project_2_singleCPU.sim\sim_1\behav\xsim\xsim.dir\xil_defaultlib\@p@c.sdb 1184 2018-11-25
project_2_singleCPU\project_2_singleCPU.sim\sim_1\behav\xsim\xsim.dir\xil_defaultlib\@p@c4.sdb 599 2018-11-25
project_2_singleCPU\project_2_singleCPU.sim\sim_1\behav\xsim\xsim.dir\xil_defaultlib\@reg@file.sdb 2045 2018-11-25
project_2_singleCPU\project_2_singleCPU.sim\sim_1\behav\xsim\xsim.dir\xil_defaultlib\@sign@zero@extend.sdb 936 2018-11-25
project_2_singleCPU\project_2_singleCPU.sim\sim_1\behav\xsim\xsim.dir\xil_defaultlib\glbl.sdb 3735 2018-11-23
project_2_singleCPU\project_2_singleCPU.sim\sim_1\behav\xsim\xsim.dir\xil_defaultlib\xil_defaultlib.rlx 4153 2018-11-25
project_2_singleCPU\project_2_singleCPU.sim\sim_1\behav\xsim\xsim.dir\xsim.svtype 12 2018-11-25
project_2_singleCPU\project_2_singleCPU.sim\sim_1\behav\xsim\xsim.ini 40 2018-11-25
project_2_singleCPU\project_2_singleCPU.sim\sim_1\behav\xsim\xvlog.log 3670 2018-11-25
project_2_singleCPU\project_2_singleCPU.sim\sim_1\behav\xsim\xvlog.pb 5964 2018-11-25
project_2_singleCPU\project_2_singleCPU.sim\sim_1\behav\xsim.ini 39 2018-06-10
project_2_singleCPU\project_2_singleCPU.srcs\sim_1\new\CPU_single_sim.v 1188 2018-11-19
project_2_singleCPU\project_2_singleCPU.srcs\sources_1\new\7_SegLED.v 1540 2018-06-10
project_2_singleCPU\project_2_singleCPU.srcs\sources_1\new\ALU.v 1571 2018-11-25
project_2_singleCPU\project_2_singleCPU.srcs\sources_1\new\ControlUnit.v 7612 2018-11-25
project_2_singleCPU\project_2_singleCPU.srcs\sources_1\new\CPU_single.v 2371 2018-11-22
project_2_singleCPU\project_2_singleCPU.srcs\sources_1\new\JUMP.v 622 2018-11-22
project_2_singleCPU\project_2_singleCPU.srcs\sources_1\new\Multiplexer32For2.v 811 2018-11-21

CodeBus www.codebus.net