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Title: Nexys4DDR-master Download
  • Category:
  • Other systems
  • Platform:
  • Verilog
  • File Size:
  • 956416
  • Update:
  • 2019-06-14
  • Downloads:
  • 0
  • Uploaded by:
  • sqkkkkk
 Description: guidebook of fpga nexys4ddr
 Downloaders recently: [More information of uploader sqkkkkk]
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File list (Click to check if it's the file you need, and recomment it at the bottom):
文件名大小更新时间
Nexys4DDR-master 0 2016-06-01
Nexys4DDR-master\.gitattributes 378 2016-06-01
Nexys4DDR-master\.gitignore 1983 2016-06-01
Nexys4DDR-master\Projects 0 2016-06-01
Nexys4DDR-master\Projects\GPIO 0 2016-06-01
Nexys4DDR-master\Projects\GPIO\proj 0 2016-06-01
Nexys4DDR-master\Projects\GPIO\proj\_READ_ME_.txt 670 2016-06-01
Nexys4DDR-master\Projects\GPIO\proj\cleanup.cmd 453 2016-06-01
Nexys4DDR-master\Projects\GPIO\proj\cleanup.sh 533 2016-06-01
Nexys4DDR-master\Projects\GPIO\proj\create_project.tcl 3786 2016-06-01
Nexys4DDR-master\Projects\GPIO\src 0 2016-06-01
Nexys4DDR-master\Projects\GPIO\src\constraints 0 2016-06-01
Nexys4DDR-master\Projects\GPIO\src\constraints\Nexys4DDR_Master.xdc 19685 2016-06-01
Nexys4DDR-master\Projects\GPIO\src\hdl 0 2016-06-01
Nexys4DDR-master\Projects\GPIO\src\hdl\GPIO_Demo.vhd 17247 2016-06-01
Nexys4DDR-master\Projects\GPIO\src\hdl\RGB_controller.vhd 5183 2016-06-01
Nexys4DDR-master\Projects\GPIO\src\hdl\UART_TX_CTRL.vhd 4590 2016-06-01
Nexys4DDR-master\Projects\GPIO\src\hdl\debouncer.vhd 3415 2016-06-01
Nexys4DDR-master\Projects\Keyboard 0 2016-06-01
Nexys4DDR-master\Projects\Keyboard\proj 0 2016-06-01
Nexys4DDR-master\Projects\Keyboard\proj\_READ_ME_.txt 670 2016-06-01
Nexys4DDR-master\Projects\Keyboard\proj\cleanup.cmd 453 2016-06-01
Nexys4DDR-master\Projects\Keyboard\proj\cleanup.sh 533 2016-06-01
Nexys4DDR-master\Projects\Keyboard\proj\create_project.tcl 3790 2016-06-01
Nexys4DDR-master\Projects\Keyboard\src 0 2016-06-01
Nexys4DDR-master\Projects\Keyboard\src\constraints 0 2016-06-01
Nexys4DDR-master\Projects\Keyboard\src\constraints\Nexys4DDR_Master.xdc 19644 2016-06-01
Nexys4DDR-master\Projects\Keyboard\src\hdl 0 2016-06-01
Nexys4DDR-master\Projects\Keyboard\src\hdl\PS2Receiver.v 1774 2016-06-01
Nexys4DDR-master\Projects\Keyboard\src\hdl\Seg_7_Display.v 2714 2016-06-01
Nexys4DDR-master\Projects\Keyboard\src\hdl\debouncer.v 1036 2016-06-01
Nexys4DDR-master\Projects\Keyboard\src\hdl\top.v 1223 2016-06-01
Nexys4DDR-master\Projects\Music_Looper_Demo 0 2016-06-01
Nexys4DDR-master\Projects\Music_Looper_Demo\proj 0 2016-06-01
Nexys4DDR-master\Projects\Music_Looper_Demo\proj\_READ_ME_.txt 670 2016-06-01
Nexys4DDR-master\Projects\Music_Looper_Demo\proj\cleanup.cmd 453 2016-06-01
Nexys4DDR-master\Projects\Music_Looper_Demo\proj\cleanup.sh 533 2016-06-01
Nexys4DDR-master\Projects\Music_Looper_Demo\proj\create_project.tcl 3860 2016-06-01
Nexys4DDR-master\Projects\Music_Looper_Demo\src 0 2016-06-01
Nexys4DDR-master\Projects\Music_Looper_Demo\src\constraints 0 2016-06-01
Nexys4DDR-master\Projects\Music_Looper_Demo\src\constraints\Nexys4DDR_Master.xdc 19701 2016-06-01
Nexys4DDR-master\Projects\Music_Looper_Demo\src\hdl 0 2016-06-01
Nexys4DDR-master\Projects\Music_Looper_Demo\src\hdl\AnalogXADC.v 1937 2016-06-01
Nexys4DDR-master\Projects\Music_Looper_Demo\src\hdl\Binary_to_BCD_B_bcdout.v 973 2016-06-01
Nexys4DDR-master\Projects\Music_Looper_Demo\src\hdl\DigitToSeg.v 2729 2016-06-01
Nexys4DDR-master\Projects\Music_Looper_Demo\src\hdl\Ram2Ddr.vhd 23714 2016-06-01
Nexys4DDR-master\Projects\Music_Looper_Demo\src\hdl\counter3bit.v 360 2016-06-01
Nexys4DDR-master\Projects\Music_Looper_Demo\src\hdl\debounce.v 2046 2016-06-01
Nexys4DDR-master\Projects\Music_Looper_Demo\src\hdl\decoder3_8.v 942 2016-06-01
Nexys4DDR-master\Projects\Music_Looper_Demo\src\hdl\loop_ctrl.v 7313 2016-06-01
Nexys4DDR-master\Projects\Music_Looper_Demo\src\hdl\looper1_1.v 12852 2016-06-01
Nexys4DDR-master\Projects\Music_Looper_Demo\src\hdl\mem_ctrl.v 7864 2016-06-01
Nexys4DDR-master\Projects\Music_Looper_Demo\src\hdl\mux4_4bus.v 866 2016-06-01
Nexys4DDR-master\Projects\Music_Looper_Demo\src\hdl\pwm_module.v 752 2016-06-01
Nexys4DDR-master\Projects\Music_Looper_Demo\src\hdl\segClkDevider.v 1045 2016-06-01
Nexys4DDR-master\Projects\Music_Looper_Demo\src\hdl\sevensegdecoder.v 1287 2016-06-01
Nexys4DDR-master\Projects\Music_Looper_Demo\src\ip 0 2016-06-01
Nexys4DDR-master\Projects\Music_Looper_Demo\src\ip\clk_wiz_0 0 2016-06-01
Nexys4DDR-master\Projects\Music_Looper_Demo\src\ip\clk_wiz_0\clk_wiz_0.upgrade_log 11160 2016-06-01
Nexys4DDR-master\Projects\Music_Looper_Demo\src\ip\clk_wiz_0\clk_wiz_0.xci 67964 2016-06-01
Nexys4DDR-master\Projects\Music_Looper_Demo\src\ip\clk_wiz_0\clk_wiz_0.xml 272901 2016-06-01
Nexys4DDR-master\Projects\Music_Looper_Demo\src\ip\mig_7series_0 0 2016-06-01
Nexys4DDR-master\Projects\Music_Looper_Demo\src\ip\mig_7series_0\mig_7series_0.vho 8053 2016-06-01
Nexys4DDR-master\Projects\Music_Looper_Demo\src\ip\mig_7series_0\mig_7series_0.xci 159256 2016-06-01
Nexys4DDR-master\Projects\Music_Looper_Demo\src\ip\mig_7series_0\mig_7series_0.xml 5780351 2016-06-01
Nexys4DDR-master\Projects\Music_Looper_Demo\src\ip\mig_7series_0\mig_7series_0 0 2016-06-01
Nexys4DDR-master\Projects\Music_Looper_Demo\src\ip\mig_7series_0\mig_7series_0\datasheet.txt 2334 2016-06-01
Nexys4DDR-master\Projects\Music_Looper_Demo\src\ip\mig_7series_0\mig_7series_0\docs 0 2016-06-01
Nexys4DDR-master\Projects\Music_Looper_Demo\src\ip\mig_7series_0\mig_7series_0\docs\phy_only_support_readme.txt 597 2016-06-01
Nexys4DDR-master\Projects\Music_Looper_Demo\src\ip\mig_7series_0\mig_7series_0\example_design 0 2016-06-01
Nexys4DDR-master\Projects\Music_Looper_Demo\src\ip\mig_7series_0\mig_7series_0\example_design\log.txt 3900 2016-06-01
Nexys4DDR-master\Projects\Music_Looper_Demo\src\ip\mig_7series_0\mig_7series_0\example_design\par 0 2016-06-01
Nexys4DDR-master\Projects\Music_Looper_Demo\src\ip\mig_7series_0\mig_7series_0\example_design\par\example_top.xdc 1214 2016-06-01
Nexys4DDR-master\Projects\Music_Looper_Demo\src\ip\mig_7series_0\mig_7series_0\example_design\par\readme.txt 824 2016-06-01
Nexys4DDR-master\Projects\Music_Looper_Demo\src\ip\mig_7series_0\mig_7series_0\example_design\rtl 0 2016-06-01
Nexys4DDR-master\Projects\Music_Looper_Demo\src\ip\mig_7series_0\mig_7series_0\example_design\rtl\example_top.vhd 33681 2016-06-01
Nexys4DDR-master\Projects\Music_Looper_Demo\src\ip\mig_7series_0\mig_7series_0\example_design\rtl\traffic_gen 0 2016-06-01
Nexys4DDR-master\Projects\Music_Looper_Demo\src\ip\mig_7series_0\mig_7series_0\example_design\rtl\traffic_gen\mig_7series_v2_3_afifo.v 6196 2016-06-01
Nexys4DDR-master\Projects\Music_Looper_Demo\src\ip\mig_7series_0\mig_7series_0\example_design\rtl\traffic_gen\mig_7series_v2_3_cmd_gen.v 35442 2016-06-01
Nexys4DDR-master\Projects\Music_Looper_Demo\src\ip\mig_7series_0\mig_7series_0\example_design\rtl\traffic_gen\mig_7series_v2_3_cmd_prbs_gen.v 10591 2016-06-01
Nexys4DDR-master\Projects\Music_Looper_Demo\src\ip\mig_7series_0\mig_7series_0\example_design\rtl\traffic_gen\mig_7series_v2_3_data_prbs_gen.v 4725 2016-06-01
Nexys4DDR-master\Projects\Music_Looper_Demo\src\ip\mig_7series_0\mig_7series_0\example_design\rtl\traffic_gen\mig_7series_v2_3_init_mem_pattern_ctr.v 39110 2016-06-01
Nexys4DDR-master\Projects\Music_Looper_Demo\src\ip\mig_7series_0\mig_7series_0\example_design\rtl\traffic_gen\mig_7series_v2_3_memc_flow_vcontrol.v 15757 2016-06-01
Nexys4DDR-master\Projects\Music_Looper_Demo\src\ip\mig_7series_0\mig_7series_0\example_design\rtl\traffic_gen\mig_7series_v2_3_memc_traffic_gen.v 32702 2016-06-01
Nexys4DDR-master\Projects\Music_Looper_Demo\src\ip\mig_7series_0\mig_7series_0\example_design\rtl\traffic_gen\mig_7series_v2_3_rd_data_gen.v 12351 2016-06-01
Nexys4DDR-master\Projects\Music_Looper_Demo\src\ip\mig_7series_0\mig_7series_0\example_design\rtl\traffic_gen\mig_7series_v2_3_read_data_path.v 28068 2016-06-01
Nexys4DDR-master\Projects\Music_Looper_Demo\src\ip\mig_7series_0\mig_7series_0\example_design\rtl\traffic_gen\mig_7series_v2_3_read_posted_fifo.v 7842 2016-06-01
Nexys4DDR-master\Projects\Music_Looper_Demo\src\ip\mig_7series_0\mig_7series_0\example_design\rtl\traffic_gen\mig_7series_v2_3_s7ven_data_gen.v 38757 2016-06-01
Nexys4DDR-master\Projects\Music_Looper_Demo\src\ip\mig_7series_0\mig_7series_0\example_design\rtl\traffic_gen\mig_7series_v2_3_tg_prbs_gen.v 11144 2016-06-01
Nexys4DDR-master\Projects\Music_Looper_Demo\src\ip\mig_7series_0\mig_7series_0\example_design\rtl\traffic_gen\mig_7series_v2_3_tg_status.v 4748 2016-06-01
Nexys4DDR-master\Projects\Music_Looper_Demo\src\ip\mig_7series_0\mig_7series_0\example_design\rtl\traffic_gen\mig_7series_v2_3_traffic_gen_top.v 29333 2016-06-01
Nexys4DDR-master\Projects\Music_Looper_Demo\src\ip\mig_7series_0\mig_7series_0\example_design\rtl\traffic_gen\mig_7series_v2_3_vio_init_pattern_bram.v 13131 2016-06-01
Nexys4DDR-master\Projects\Music_Looper_Demo\src\ip\mig_7series_0\mig_7series_0\example_design\rtl\traffic_gen\mig_7series_v2_3_wr_data_gen.v 13246 2016-06-01
Nexys4DDR-master\Projects\Music_Looper_Demo\src\ip\mig_7series_0\mig_7series_0\example_design\rtl\traffic_gen\mig_7series_v2_3_write_data_path.v 7212 2016-06-01
Nexys4DDR-master\Projects\Music_Looper_Demo\src\ip\mig_7series_0\mig_7series_0\example_design\sim 0 2016-06-01
Nexys4DDR-master\Projects\Music_Looper_Demo\src\ip\mig_7series_0\mig_7series_0\example_design\sim\ddr2_model.v 111040 2016-06-01
Nexys4DDR-master\Projects\Music_Looper_Demo\src\ip\mig_7series_0\mig_7series_0\example_design\sim\ddr2_model_parameters.vh 111439 2016-06-01
Nexys4DDR-master\Projects\Music_Looper_Demo\src\ip\mig_7series_0\mig_7series_0\example_design\sim\ies_run.sh 5413 2016-06-01
Nexys4DDR-master\Projects\Music_Looper_Demo\src\ip\mig_7series_0\mig_7series_0\example_design\sim\readme.txt 9303 2016-06-01
Nexys4DDR-master\Projects\Music_Looper_Demo\src\ip\mig_7series_0\mig_7series_0\example_design\sim\sim.do 6536 2016-06-01

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