Welcome![Sign In][Sign Up]
Location:
Downloads SourceCode/Document Embeded-SCM Develop VHDL-FPGA-Verilog
Title: parameter_UART_RX Download
 Description: I had uploaded a serial port receiving module, but a file was indeed missed. This time, I will send it again. Modified PARITY_ Check module, which can support the application without parity. The serial port receiving module can use parameter to configure the transmission rate, transmission bit width and verification. Using Verilog voice programming. Users can configure parameters according to the requirements of serial port, and configure FIFO according to the size of buffer. The frame error (stop bit is not high), check error and read FIFO timeout (when FIFO is full, there is new data to) are checked.
 Downloaders recently: [More information of uploader 老工程师]
 To Search:
File list (Click to check if it's the file you need, and recomment it at the bottom):
文件名大小更新时间
parameter_UART_RX\BPS_CV_GEN.v 1129 2017-07-19
parameter_UART_RX\DIV16_CNT.v 902 2017-07-19
parameter_UART_RX\PARITY_CHECK.v 523 2020-05-23
parameter_UART_RX\RXD_SEEKER.v 1747 2017-07-19
parameter_UART_RX\START_BIT_CHECK.v 997 2017-07-11
parameter_UART_RX\UART_RX_MODULE.v 2449 2020-05-23
parameter_UART_RX\UART_USER_MOD.v 3435 2020-05-23
parameter_UART_RX 0 2020-05-23

CodeBus www.codebus.net