Description: Direct digital frequency synthesizer, using ROM compression method, validation and AISC through FPGA Implementation
To Search:
- [des1] - From the description of the database und
- [FPG] - FPGA-based board-level BIST design and i
File list (Check if you may need any files):
DDFS_verilog\DDFS.v
............\freq_adder.v
............\freq_random.v
............\phase_cos.txt
............\phase_sin.txt
............\phas_gene.v
............\tb_ddfs.v
DDFS_verilog
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