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Location : Home Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
  • Category : VHDL-FPGA-Verilog
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  • Update : 2012-11-26
  • Size : 795kb
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  • Author :x****
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Introduction - If you have any usage issues, please Google them yourself
Simple sinusoidal signal generator. Design of functional modules using lpm.
Packet file list
(Preview for download)
SINGT\DATA_ROM.cmp
.....\DATA_ROM.hex
.....\DATA_ROM.vhd
.....\db\altsyncram_59e1.tdf
.....\..\altsyncram_8vj2.tdf
.....\..\decode_aoi.tdf
.....\..\mux_cnc.tdf
.....\..\SINGT.asm.qmsg
.....\..\SINGT.asm_labs.ddb
.....\..\SINGT.cbx.xml
.....\..\SINGT.cmp.cdb
.....\..\SINGT.cmp.hdb
.....\..\SINGT.cmp.kpt
.....\..\SINGT.cmp.logdb
.....\..\SINGT.cmp.rdb
.....\..\SINGT.cmp.tdb
.....\..\SINGT.cmp0.ddb
.....\..\SINGT.cmp2.ddb
.....\..\SINGT.dbp
.....\..\SINGT.db_info
.....\..\SINGT.eco.cdb
.....\..\SINGT.eds_overflow
.....\..\SINGT.fit.qmsg
.....\..\SINGT.fnsim.cdb
.....\..\SINGT.fnsim.hdb
.....\..\SINGT.fnsim.qmsg
.....\..\SINGT.hier_info
.....\..\SINGT.hif
.....\..\SINGT.map.cdb
.....\..\SINGT.map.hdb
.....\..\SINGT.map.logdb
.....\..\SINGT.map.qmsg
.....\..\SINGT.pre_map.cdb
.....\..\SINGT.pre_map.hdb
.....\..\SINGT.psp
.....\..\SINGT.rtlv.hdb
.....\..\SINGT.rtlv_sg.cdb
.....\..\SINGT.rtlv_sg_swap.cdb
.....\..\SINGT.sgdiff.cdb
.....\..\SINGT.sgdiff.hdb
.....\..\SINGT.signalprobe.cdb
.....\..\SINGT.sim.hdb
.....\..\SINGT.sim.qmsg
.....\..\SINGT.sim.rdb
.....\..\SINGT.sim.vwf
.....\..\SINGT.sld_design_entry.sci
.....\..\SINGT.sld_design_entry_dsc.sci
.....\..\SINGT.syn_hier_info
.....\..\SINGT.tan.qmsg
.....\..\wed.zsf
.....\SINGT.asm.rpt
.....\SINGT.done
.....\SINGT.fit.rpt
.....\SINGT.fit.smsg
.....\SINGT.fit.summary
.....\SINGT.flow.rpt
.....\SINGT.map.rpt
.....\SINGT.map.summary
.....\SINGT.pin
.....\SINGT.pof
.....\SINGT.qpf
.....\SINGT.qsf
.....\SINGT.qws
.....\SINGT.sim.rpt
.....\SINGT.sof
.....\SINGT.tan.rpt
.....\SINGT.tan.summary
.....\SINGT.vhd
.....\SINGT.vwf
.....\db
SINGT
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