VHDL-FPGA-Verilog List Page 3044

VHDL-FPGA-Verilog list

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aes_package Downloaded：0: This Module defines all the functions and Signals used at various instances in the algorithm in a package
Date : 2025-11-17 Size : 4kb User : Syed Shafi
aes_decrypt Downloaded：0: This is the Top Module for AES Decryption algorithm
Date : 2025-11-17 Size : 3kb User : Syed Shafi
test_dec1 Downloaded：0: This Module creates the test Bench for AES Decryption Algorithm
Date : 2025-11-17 Size : 1kb User : Syed Shafi
eda Downloaded：0: ATMEL Corporation QUETUSii using software written in verilog language program, the realization of a zone reset, adjust the time function of the electronic clock to digital display of time, adjusting time to adjust bit fl
Date : 2025-11-17 Size : 1.52mb User : 秦玉龙
FPGA_diaodianbaocunchegnxu Downloaded：0: FPGA power-down save the program for fpga power-down procedures for how to save after
Date : 2025-11-17 Size : 184kb User : wjz
asyncwrite Downloaded：0: FPGA asynchronous transfer timing synchronization timing module Width (bit)
Date : 2025-11-17 Size : 1kb User : 赵栩
zy4668_ybcxjk Downloaded：0: The source VHDL implementation of the function is the preparation of Asynchronous Serial Interface
Date : 2025-11-17 Size : 2.56mb User : 张楠
zy4668_music Downloaded：0: This source code implements the design using VHDL language music player
Date : 2025-11-17 Size : 3.22mb User : 张楠
ADPCMCodec Downloaded：0: The DVI Adaptive Differential Pulse Code Modulation (ADPCM) algorithm was first described in an IMA recommendation on audio formats and conversion practices [1]. ADPCM is a transformation that encodes 16-bit audio as 4 b
Date : 2025-11-17 Size : 429kb User : stefanescul
ManchesterEncoding Downloaded：0: Manchester Encoding based on FPGA
Date : 2025-11-17 Size : 332kb User : willam
pci_interface Downloaded：0: pci interface verilog
Date : 2025-11-17 Size : 12kb User : willam
Verilog_design_135_classic_example Downloaded：0: Verilog design 135 classic example
Date : 2025-11-17 Size : 111kb User : 马海兵

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