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[File OperateFPGA_27eg

Description: FPGA很有价值的27实例.rar 包括 LED控制VHDL程序与仿真 2004.8修改.doc; LED控制VHDL程序与仿真; LCD控制VHDL程序与仿真 2004.8修改; LCD控制VHDL程序与仿真; ADC0809 VHDL控制程序; TLC5510 VHDL控制程序; DAC0832 接口电路程序; TLC7524接口电路程序; URAT VHDL程序与仿真; ASK调制与解调VHDL程序及仿真; FSK调制与解调VHDL程序及仿真; PSK调制与解调VHDL程序及仿真; MASK调制VHDL程序及仿真; MFSK调制VHDL程序及仿真; MPSK调制与解调VHDL程序与仿真; 基带码发生器程序设计与仿真; 频率计程序设计与仿真; 采用等精度测频原理的频率计程序与仿真; 电子琴程序设计与仿真 2004.8修改; 电子琴程序设计与仿真; 电梯控制器程序设计与仿真; 电子时钟VHDL程序与仿真; 自动售货机VHDL程序与仿真; 出租车计价器VHDL程序与仿真 2004.8修改; 出租车计价器VHDL程序与仿真; 波形发生程序; 步进电机定位控制系统VHDL程序与仿-FPGA value of the 27 examples. Rar including LED control procedures and VHDL simulation 200 4.8 amendments. doc; LED control procedures and VHDL simulation; LCD control procedures and VHDL simulation 2004.8 modified; LCD control procedures and VHDL simulation; Connection between ADC 0809 VHDL control procedures; TLC5510 VHDL control procedures; DAC0832 interface circuits; TLC7524 interface circuits; URAT procedures and VHDL simulation; ASK modulation and demodulation process and VHDL simulation; FSK modulation and demodulation process and VHDL simulation; PSK modulation and demodulation process and VHDL simulation; MASK modulation procedures and VHDL simulation; MFSK modulation procedures and VHDL simulation; MPSK modulation and demodulation process and VHDL simulation; Base-band code gene
Platform: | Size: 1279333 | Author: | Hits:

[VHDL-FPGA-VerilogLED.VHDL

Description: LED控制VHDL程序与仿真 分别介绍采用FPGA对LED进行静态和动态显示的数字时钟控制程序-LED control procedures and VHDL simulation briefed on the use of FPGA LED static and dynamic significantly the figures show clock control procedures
Platform: | Size: 5120 | Author: 少龙 | Hits:

[File FormatFPGA_27eg

Description: FPGA很有价值的27实例.rar 包括 LED控制VHDL程序与仿真 2004.8修改.doc; LED控制VHDL程序与仿真; LCD控制VHDL程序与仿真 2004.8修改; LCD控制VHDL程序与仿真; ADC0809 VHDL控制程序; TLC5510 VHDL控制程序; DAC0832 接口电路程序; TLC7524接口电路程序; URAT VHDL程序与仿真; ASK调制与解调VHDL程序及仿真; FSK调制与解调VHDL程序及仿真; PSK调制与解调VHDL程序及仿真; MASK调制VHDL程序及仿真; MFSK调制VHDL程序及仿真; MPSK调制与解调VHDL程序与仿真; 基带码发生器程序设计与仿真; 频率计程序设计与仿真; 采用等精度测频原理的频率计程序与仿真; 电子琴程序设计与仿真 2004.8修改; 电子琴程序设计与仿真; 电梯控制器程序设计与仿真; 电子时钟VHDL程序与仿真; 自动售货机VHDL程序与仿真; 出租车计价器VHDL程序与仿真 2004.8修改; 出租车计价器VHDL程序与仿真; 波形发生程序; 步进电机定位控制系统VHDL程序与仿-FPGA value of the 27 examples. Rar including LED control procedures and VHDL simulation 200 4.8 amendments. doc; LED control procedures and VHDL simulation; LCD control procedures and VHDL simulation 2004.8 modified; LCD control procedures and VHDL simulation; Connection between ADC 0809 VHDL control procedures; TLC5510 VHDL control procedures; DAC0832 interface circuits; TLC7524 interface circuits; URAT procedures and VHDL simulation; ASK modulation and demodulation process and VHDL simulation; FSK modulation and demodulation process and VHDL simulation; PSK modulation and demodulation process and VHDL simulation; MASK modulation procedures and VHDL simulation; MFSK modulation procedures and VHDL simulation; MPSK modulation and demodulation process and VHDL simulation; Base-band code gene
Platform: | Size: 1278976 | Author: | Hits:

[VHDL-FPGA-VerilogVHDL

Description: 采用VHDL语言设计一个4通道的数据采集控制模块。系统的功能描述如下: 1.系统主时钟为100 MHz。 2.数据为16位-数据线上连续2次00FF后数据传输开始。 3.系统内部总线宽度为8位。 4.共有4个通道(ch1、ch2、ch3、ch4),每个通道配备100 Bytes的RAM,当存满数据后停止数据采集并且相应通道的状态位产生报警信号。 5.数据分为8位串行输出,输出时钟由外部数据读取电路给出。 6.具备显示模块驱动功能。由SEL信号设置显示的通道,DISPLAY信号启动所选通道RAM中数值的显示过程。数值顺次显示一遍后显示结束,可以重新设定SEL的值选择下一个通道。模块数据线为8位,显示器件为4个8段LED。 7.数据采集模式如下:单通道采集(由SEL信号选择通道),多通道顺次采集(当前通道采满后转入下一通道),多通道并行采集(每通道依次采集一个数据)。模式由控制信号MODE选择,采集数据的总个数由NUM_COLLECT给出。 8.数据采集过程中不能读取,数据读取过程中不能采集-err
Platform: | Size: 5782528 | Author: pengfu | Hits:

[SCMmiaobiao.RAR

Description: 实验采用七段码LED设计(数码管),显示直观;采用定时器中断,计时更准确;功能齐全,可随时启动、停止、清零,后者智能化程度更高。-Seven-Segment LED code using the experimental design (digital control), visual display using timer interrupt, a more accurate time functions, may at any time to start, stop, cleared, and the latter an even higher degree of intelligence.
Platform: | Size: 33792 | Author: cuipinpin | Hits:

[VHDL-FPGA-Verilogkey_4x4

Description: 4x4键盘结合LED动态显示,里面包含了键盘扫描、2进制转10进制BCD码、LED编码和LED动态显示-4x4 keyboard combination LED dynamic display, which contains the keyboard scan, 2 to 10 hexadecimal BCD hex code, LED codes and LED dynamic display
Platform: | Size: 134144 | Author: hao | Hits:

[VHDL-FPGA-Verilogsong

Description: module song(clk,key,song_out,led) input [7:0] key input clk output song_out output [7:0] led reg song_reg reg [21:0] count reg [19:0] delay reg [7:0] key_reg always @(posedge clk) begin count=count+1 if((count==delay)&(!(delay==20 d65535))) begin count=22 d0 song_reg=!song_reg end end always @(key) begin key_reg=key case(key_reg) 8 b0000_0001: delay=20 d47774 //zhong yin 1 523.3HZ 8 b0000_0010: delay=20 d42568 //zhong yin 2 587.3HZ 8 b0000_0100: delay=20 d37919 //zhong yin 3 659.3HZ 8 b0000_1000: delay=20 d35791 //zhong yin 4 698.5HZ 8 b0001_0000: delay=20 d31888 //zhong yin 5 784HZ 8 b0010_0000: delay=20 d28409 //zhong yin 6 880HZ 8 b0100_0000: delay=20 d25309 //zhong yin 7 987.8HZ 8 b1000_0000: delay=20 d23889 //gao yin 1 1046.5HZ default: delay=20 d65535 endcase end assign song_out=song_reg 文件: song.rar 大小: 357KB 下载: 下载 assign led=key_reg endmodule -module song (clk, key, song_out, led) input [7:0] key input clk output song_out output [7:0] led reg song_reg reg [21:0] count reg [19:0 ] delay reg [7:0] key_reg always @ (posedge clk) begin count = count+1 if ((count == delay )& (!( delay == 20' d65535))) begin count = 22 ' d0 song_reg =! song_reg end end always @ (key) begin key_reg = key case (key_reg) 8' b0000_0001: delay = 20' d47774 // zhong yin 1 523.3HZ 8' b0000_0010: delay = 20' d42568 // zhong yin 2 587.3HZ 8' b0000_0100: delay = 20' d37919 // zhong yin 3 659.3HZ 8' b0000_1000: delay = 20' d35791 // zhong yin 4 698.5HZ 8' b0001_0000: delay = 20' d31888 // zhong yin 5 784HZ 8' b0010_0000: delay = 20' d28409 // zhong yin 6 880HZ 8' b0100_0000: delay = 20' d25309 // zhong yin 7 987.8HZ 8' b1000_0000: delay = 20' d23889 // gao yin 1 1046.5HZ default: delay = 20' d65535 endcase end assign song_out = song_reg file: song.rar Size: 357KB Download: Download
Platform: | Size: 365568 | Author: 罗仲景 | Hits:

[Embeded-SCM DevelopDE0_PWM_LED

Description: 利用pwm做出的一个控制led亮度的小程序!-Pwm to make use of a control led brightness applet!
Platform: | Size: 15360 | Author: tony | Hits:

[VHDL-FPGA-Verilogelecfans.com-

Description: FPGA很有价值的27实例.rar 包括 LED控制VHDL程序与仿真 2004.8修改.doc-vhdl example
Platform: | Size: 491520 | Author: 徐鹏支 | Hits:

[VHDL-FPGA-Verilogledtest

Description: 数码管译码电路的测试程序,使用modlesim进行测试。该文件和led.rar配合测试使用,如果不需要测试,无需下载该文件。led.rar使用的是模块化设计,分为几个vhdl文件。-Digital decoding circuit test program, using modlesim tested. The documents and led.rar with testing, if you do not test, without having to download the file. led.rar using a modular design, vhdl divided into several files.
Platform: | Size: 62464 | Author: 10086 | Hits:

[Other Embeded programeda.rar

Description: 课程设计-交通灯控制系统的设计帮助理解EDA课程中VHDL语言(Curriculum design - traffic lights control system design to help understand the EDA course VHDL language)
Platform: | Size: 245760 | Author: cainiaolaoda | Hits:

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